IndieSemiC & Semtech Launch ‘Sabarmati-1’ RISC-V & LoRa SiP, Shifting IoT Chip Dynamics

đź“°Original Source: ETTelecomIndieSemiC & Semtech Launch ‘Sabarmati-1’ RISC-V & LoRa SiP, Shifting IoT Chip Dynamics Source: ETTelecom, reporting on a July 27, 2026 announcement from Ahmedabad, India. Gujarat-based semiconductor startup IndieSemiC Pvt. Ltd. has announced a strategic partnership with US-based IoT connectivity leader Semtech Corporation…

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đź“°Original Source: ETTelecom

IndieSemiC & Semtech Launch ‘Sabarmati-1’ RISC-V & LoRa SiP, Shifting IoT Chip Dynamics

Source: ETTelecom, reporting on a July 27, 2026 announcement from Ahmedabad, India.

Gujarat-based semiconductor startup IndieSemiC Pvt. Ltd. has announced a strategic partnership with US-based IoT connectivity leader Semtech Corporation to co-develop the “Sabarmati-1,” a 64-bit RISC-V-based System-in-Package (SiP) with integrated LoRa connectivity. This collaboration, backed by India’s Semiconductor Mission (ISM), marks a significant development in the global IoT silicon landscape, directly impacting telecom operators and network infrastructure providers by potentially lowering the cost and complexity of deploying massive-scale, low-power IoT networks. The move signals India’s growing ambition to become a design and manufacturing hub for specialized telecom and IoT chips, challenging the dominance of established ARM-based architectures and creating new supply chain options for network equipment vendors and IoT service providers.

Technical Deep Dive: The Sabarmati-1 SiP Architecture

Aerial view of Ahmedabad showcasing the Sabarmati River and city skyline under a clear sky.
Photo by Shlok

The Sabarmati-1 represents a convergence of two pivotal open-source and open-standard movements in the semiconductor and wireless industries: the RISC-V instruction set architecture (ISA) and the LoRaWAN protocol. The chip is designed as a highly integrated SiP, a packaging technology that combines multiple dies—like a processor, memory, and RF transceiver—into a single module. According to the announcement, the core specifications include:

  • Processor: A 64-bit RISC-V application-class CPU core, providing an open-standard alternative to proprietary architectures from ARM or proprietary microcontroller units (MCUs). This offers design freedom and potential cost savings by avoiding architecture licensing fees.
  • Connectivity: Integrated Semtech LoRa transceiver, supporting sub-GHz frequencies (e.g., 868 MHz in EU, 915 MHz in US, 433 MHz in ASIA) used for LoRaWAN networks. This enables long-range communication (over 10 km in rural areas) with very low power consumption, ideal for battery-operated sensors.
  • Form Factor: System-in-Package (SiP) design, which reduces the board footprint, simplifies device manufacturing for OEMs, and improves reliability compared to discrete component layouts.
  • Target Applications: Smart agriculture sensors, asset tracking, industrial monitoring, smart city infrastructure (e.g., waste management, parking, lighting), and utilities (smart metering for water and gas).

The “Sabarmati-1” name, referencing the river in Gujarat, underscores its origins within India’s burgeoning semiconductor design ecosystem. The development is supported under the India Semiconductor Mission’s “Design-Linked Incentive (DLI)” scheme, part of the broader “Semiconductor Policy 2022-27,” which provides financial and infrastructure support for domestic chip design.

Industry Impact: Reshaping the IoT Device and Network Ecosystem

Four students work together on a laptop, preparing a presentation indoors by a chalkboard.
Photo by Shibraj Deb

The introduction of a cost-optimized, RISC-V + LoRa SiP has immediate and long-term implications for the telecom IoT value chain, from chip vendors to mobile network operators (MNOs) and tower companies.

For IoT Module and Device OEMs: The Sabarmati-1 SiP promises a simplified bill of materials (BOM) and reduced time-to-market. By integrating the application processor and LoRa RF front-end, device manufacturers can design smaller, more power-efficient end-points. The open nature of RISC-V may also foster a more diverse ecosystem of software development tools and real-time operating systems (RTOS), potentially driving down overall solution costs. This directly competes with established solutions like Semtech’s own LoRa chipsets paired with ARM Cortex-M MCUs from vendors like STMicroelectronics or NXP.

For Telecom Network Operators (MNOs & LPWAN Operators): Lower device costs are a primary catalyst for massive IoT adoption. Operators deploying or managing LoRaWAN networks—either as public network operators (like Tata Communications’ LoRa network in India) or private network integrators for enterprises—will benefit from a wider variety of affordable sensor endpoints. This makes IoT service offerings more competitive against cellular IoT technologies like NB-IoT and LTE-M, especially in use cases where ultra-low cost and long battery life are paramount over mobility or high data rates. It also strengthens the business case for deploying or densifying LoRaWAN gateway infrastructure.

For the Global Semiconductor Supply Chain: This partnership diversifies the geographic and architectural sourcing for critical IoT components. As geopolitical tensions highlight the risks of concentrated chip manufacturing in specific regions, a design-and-potentially-fabricate initiative in India offers an alternative. If IndieSemiC scales production, it could create a new, reliable supply channel for global IoT device makers, mitigating risks associated with single-source suppliers.

Strategic Implications for India and the Global South

Scenic view of Ahmedabad's river promenade with smog overhead, showcasing urban architecture.
Photo by Ranjeet Chauhan

This announcement is not merely a product launch; it is a strategic move aligned with India’s national technological sovereignty goals and has resonance across developing telecom markets in Africa, Southeast Asia, and the Middle East.

India’s Semiconductor Ambition: The Sabarmati-1 is a tangible output of India’s $10 billion semiconductor incentive package. It demonstrates a focus on “fabless” design innovation in high-growth, specialized segments like telecom/IoT, rather than competing directly in the bleeding-edge logic chip race dominated by TSMC, Samsung, and Intel. Success here could position India as a global RISC-V design center and a hub for “IoT-for-development” solutions tailored to the needs of emerging economies—such as low-cost agricultural sensors, water quality monitors, and distributed energy management systems.

Model for Africa and MENA Regions: Many nations in Africa and the Middle East are aggressively deploying IoT for smart city and utility management. A locally-designed (or Global South-designed), cost-effective chip solution could be politically and economically attractive. It offers a path to reduce dependency on imported technology and fosters local innovation ecosystems. Partnerships between a company like IndieSemiC and regional telecom operators or system integrators could emerge, customizing SiP designs for specific regional frequency bands or environmental conditions (e.g., extreme heat tolerance).

Convergence with Satellite IoT: LoRa’s long-range capability is a key enabler for direct-to-satellite IoT services, as demonstrated by initiatives like Lacuna Space and Sateliot. A highly integrated, low-power RISC-V/LoRa chip is an ideal candidate for next-generation satellite IoT terminals. This opens a future pathway where Indian-designed chips power not just terrestrial networks but also hybrid terrestrial-satellite IoT constellations, a area of intense interest for providing coverage in remote regions across Africa, South America, and Asia.

Forward-Looking Analysis: The Telecom IoT Silicon Roadmap

Concrete bridge structure spans river in Ahmedabad, India with urban backdrop.
Photo by Ranjeet Chauhan

The IndieSemiC-Semtech collaboration is a bellwether for broader trends in telecom infrastructure silicon. We anticipate three key developments over the next 2-3 years:

  1. Architectural Wars in Edge Silicon: RISC-V will make significant inroads in the low-power, connected device segment, challenging ARM’s dominance. This will lead to more competitive pricing, greater customization, and innovation in edge AI capabilities integrated with LPWAN connectivity.
  2. Vertical Integration in Network Equipment: Major network infrastructure vendors (e.g., Nokia, Ericsson, Huawei) may explore in-house or partnership-based chip designs for their IoT gateway and core network elements, using RISC-V for control plane processing to reduce costs and increase supply chain resilience.
  3. Hybrid Connectivity Chips: The next evolution will be multi-mode SiPs that integrate LoRa with other LPWAN technologies (like NB-IoT) or short-range radios (like BLE), managed by a RISC-V core. This will create universal IoT endpoints that can dynamically select the most optimal network, simplifying deployment for operators and enterprises.

For telecom operators and infrastructure investors, the message is clear: the underlying silicon of the IoT revolution is becoming more open, diversified, and geopolitically distributed. Engaging with these new design ecosystems and supply chains will be crucial for building cost-effective, scalable, and resilient IoT networks of the future. The success of the Sabarmati-1 will be a critical test case for this new paradigm.